Patents

Patent number: 8239818

Abstract: A system and associated data structure that can be utilized within a chip design platform to define the structure of an MBIST architecture. A system for generating a memory built in self test (MBIST) design file in described, including a tool for processing an organization file (Org File), wherein the Org File includes lines of code that dictate a structure of the MBIST design file and conform to a data structure defined by the tool; wherein said data structure provides an infrastructure to describe: associations between MBIST components at a design level; associations between MBIST components and hierarchical test ports at the design level; and a serial order of daisy chains among MBIST components within the design level.

• Type: Grant

• Filed: April 5, 2011

• Date of Patent: August 7, 2012

• Assignee: International Business Machines Corporation

• Inventors: Craig M. Monroe, Michael R. Ouellette, Douglas E. Sprague, Georgy S. Varghese

Patent number: 8595678

Patent number: 8595678

Abstract: Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks.

• Type: Grant

• Filed: February 3, 2012

• Date of Patent: November 26, 2013

• Assignee: International Business Machines Corporation

• Inventors: Craig M. Monroe, Michael R. Ouellette, Douglas E. Sprague, Michael A. Ziegerhofer

Patent number: 9286181

Abstract: A method to produce a description file of Joint Test Action Group (JTAG) capture-shift test data registers to be used to interpret a test result of a memory included in an integrated circuit structure that is configured for testing integrated circuit memory. A computer extracts, from a first data file, the names a memory built in self test instance, a memory built in self test port name, and a name of a first memory. The first data file controls the hierarchical and architectural arrangement of components of an integrated circuit. The first data file describes a hierarchical order of an architectural arrangement of the components, electrical pathways, and connections between the components and the electrical pathways of an integrated circuit design. The computer adds the extracted names into the description file such that the description file is configured to interpret a test result of a memory.

• Type: Grant

• Filed: July 31, 2013

• Date of Patent: March 15, 2016

• Assignee: GLOBALFOUNDRIES INC.

• Inventors: Craig M. Monroe, Michael R. Ouellette, Douglas E. Sprague, Michael A. Ziegerhofer

Patent number: 8661399

Abstract: Aspects of the invention provide for creating a built-in-self-test (BIST) organizational file for an integrated circuit (IC) chip. In one embodiment, a method includes: receiving a design file including a hierarchy of memory modules, each module including a plurality of memory wrappers; scanning each memory wrapper in each hierarchical level of memory modules for a BIST type; creating, based on the hierarchical level and the BIST type, an ordered list of memory wrappers; adding, based on the BIST type, a BIST engine for each memory wrapper listed in the ordered list; and adding a plurality of references statements to the ordered list to create the BIST organizational file.

• Type: Grant

• Filed: August 6, 2012

• Date of Patent: February 25, 2014

• Assignee: International Business Machines Corporation

• Inventors: Craig M. Monroe, Michael R. Ouellette, Douglas E. Sprague