Processor Diagnostics Engineer (IBM Systems Group)

  • Focal point for analyzing and processing all P & Z CPU stress and field fails within the Product Engineering (PE) team

  • Excellent track record for quality & completeness of work, used in downstream analysis by the Product Failure Analysis hardware team

  • Highly skilled in Python, Pycharm IDE, Pandas, SQL for DB2, Plotly, and JupyterLab notebooks for data analysis and reporting

  • Designed, coded & deployed a Dash page in Python used for real-time, interactive analysis of chip layer failure trends utilizing Physically Aware Modus logic simulation data stored in DB2

  • Experienced with the Cadence Modus DFT software tool for simulation and analysis of both Scan

  • Chain (XOR) and Logic (ATPG) failures

(2019 – present)

Operating System Provisioning Engineer/Architect (IBM GTS IS)

  • Maintained, enhanced & supported IBM’s AIX Global Image development processes & associated automation code (Shell Script, Perl & Chef) using an Agile development flow

  • Provided customers an easy to use yet powerful method for AIX Image deployment for either RTE or mksysb based builds, along with their choice of security hardening and OS customizations

  • Developed & maintained AIX Global Images & lppsources for supported AIX TL & SP levels

  • Delivered AIX mksysb images for all major TL releases, enabling customer cloud or on-prem deployment

  • Developed and provided custom AIX images, as required, per customer specifications

  • Provided technical support for the worldwide GTS IS AIX Global Image customer base

(2013 – 2019)

Software Engineer / ASIC Test Methodology (IBM STG)

  • Developed, tested, and delivered a full suite of user friendly tools and support code written in object-oriented Perl code for enabling ASIC and Foundry customers to perform Memory BIST

  • Insertion & Verification on their chip designs using Atrenta SpyGlass

  • Coded additional complex scripts based on the core MBIST “Org” file format to provide customers with useful ancillary functions, such as Automated System Connections and Logic Simulation Test-bench generation

  • Trained internal and external customers on the end to end Memory BIST flow

  • Provided customer support for the Memory BIST flow for all customers

  • Co-authored a total of 4 Patents pertaining to the Memory BIST Methodology, the “Org” file that describes the user’s BIST architecture, and the algorithms that comprise the steps in the flow

  • Architected and coded a fully automated, reliable and flexible Regression Test System for the critical ASIC Front End Processing design flow

  • Developed and enhanced a number of Methodology design flows used by ASIC customers under IBM’s common “TheGuide” nutshell based environment making extensive use of TCL and XML

(2006 – 2013)


  • Technical Team Lead for ASIC Verilog simulation library model development for all active Standard Cell, Gate Array, and I/O technology libraries

  • Developed, enhanced and maintained a wide range of Custom Software Automation Tools

  • (mainly in C/C++, Perl & Korn-shell) to handle model generation, pattern generation, functional and SDF timing verification & more

  • Models included mainly Verilog HDL gate-level coding style with full timing, along with IP for many complex behavioral custom I/Os, latches (LSSD and industry standard), and various macros

  • Provided technical support to IBM’s ASIC customers for Verilog models & simulation issues

  • Primary Inventor on a U.S. Patent for “Multi-Valued or Single Strength Signal Detection in a Hardware Description Language” in October, 2003

  • Coded and verified custom Zycad hardware acceleration logic models from circuit schematics for the PowerPC 615 Microprocessor project

(1992 – 2006)

CIM Systems Programmer (United Engineers, Inc)

  • Part of a team of software engineers involved in the development of a Computer Integrated Manufacturing system for IBM

  • Designed and coded semiconductor tool connect software in C

  • Developed, Tested and Integrated enhancements into an existing manufacturing line support system on an OS/2 platform

(1991 - 1992)

Software Engineer (Tyrel Corporation)

  • Enhanced and maintained a large C program

  • Designed stand-alone support programs in Microsoft C including user-friendly interactive programs and MS-DOS device drivers

(1990 - 1991)